1. Field
Integrated circuit processing.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and/or receive signals external to the device(s). Common types of interconnections include copper and copper alloy interconnections (lines) connected to individual devices, including other interconnections (lines) by interconnections through vias.
One method of forming an interconnection, particularly a copper interconnection, is a damascene process. A typical damascene process involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection. The via and trench are then lined with a barrier layer of a refractory material, such as titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), or tantalum nitride (TaN). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, an adhesion layer may be formed on the barrier layer to improve the adhesion of a subsequently formed conductive interconnection to the barrier layer or the via and/or trench. Suitable materials for an adhesion layer include titanium (Ti), tantalum (Ta) and ruthenium (Ru). Next, a suitable seed material is deposited on the walls of the via and trench. Suitable seed materials for the deposition of copper interconnection material include copper (Cu), nickel (Ni), cobalt (Co), and ruthenium (Ru). Next, interconnection material, such as copper, is introduced by electroplating in a sufficient amount to fill the via and trench and complete the interconnect structure. Once introduced, the interconnection structure may be planarized and a dielectric material (including an interlayer dielectric material) introduced over the interconnection structure to suitably isolate the structure.
In prior art integrated circuit structures, a common dielectric material for use to form dielectric layers between the device and between interconnection lines was silicon dioxide (SiO2). More recent efforts are focused at minimizing the effective dielectric constant of an interlayer dielectric (ILD) so materials having a dielectric constant lower than SiO2 have gathered significance consideration. Many of these materials such as carbon doped oxide (CDO) are porous.
In order to target low dielectric constants, ILD film porosity is typically targeting excess of 30 percent by volume. Unfortunately, the highly porous materials are susceptible to penetration of metals during interconnect formation and the presence of metals within an ILD is expected to cause increased rates of failure (e.g., dielectric breakdown, high leakage).
Current methods to inhibit penetration of metal into a porous ILD include efforts to seal the surface of the pores prior to metallization. Unfortunately, these methods are not able to cover sufficiently large pore sizes, are not able to withstand necessary thermal processing, or tend to increase the total dielectric constant of the ILD.